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MONDAY | TUESDAY | WEDNESDAY | THURSDAY | FRIDAY


Speaker's Breakfast will be in Room 1A at 7:30 am Tuesday, Wednesday and Thursday.
THURSDAY
Ses# Session 36 Session 37 Session 38 Session 39 Session 40 HoT
8:30 to 10:00 Special Session: BioMEM's Panel: Will Moore's Law Rule in the Land of Analog Floorplanning Issues in Timing Analysis Special Session: ISSCC Highlights
BREAK 10:15 - 10:30 am
Ses# Session 41 Session 42 Session 43 Session 44 Session 45
10:30 to 12:00 Special Session: Multiprocessor SoC MPSoC Solutions/Nightmare Panel: Is Statistical Timing Statically Significant? Timing Issues in Placement Design Methodologies for ASIPs FPGA-Based Systems
KEYNOTE - EDA Industry Growth - Are There Enough New Problems to Solve?
12:45 - 1:45 | Ballroom 20ABC
 Walden C.Rhines, Chairman, EDA Consortium
Chairman and CEO, Mentor Graphics, Corp., Willsonville, OR
Ses# Session 46 Session 47 Session 48 Session 49 Session 50 HoT
2:00 to 4:00 Special Session: Security: A New Dimension in Embedded System Design Leakage Power Optimization Interconnect Extraction New Frontiers in Logic Synthesis Numerical Techniques for Simulation
BREAK 4 - 4:30 pm
Ses# Session 51 Session 52 Session 53 Session 54 Session 55
4:30 to 6:00 Energy and Thermal-Aware Design Noise-Tolerant Design and Analysis Techniques New Tools and Methods for Future Embedded SoC New Scan-Based Test Techniques CAD for Reconfigurable Computing